The present invention relates to the art of electronic packaging and more specifically relates to assemblies incorporating microelectronic devices such as semiconductor chips, methods of making such assemblies, and components for making the same.
Modern electronic devices utilize semiconductor integrated circuits or xe2x80x9cchipsxe2x80x9d which incorporate numerous electronic components. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip. Alternatively, in a so-called xe2x80x9chybrid circuitxe2x80x9d or xe2x80x9cmodulexe2x80x9d, one or more chips are mounted to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted on the substrate. In each case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The electrical interconnections may include numerous input/output or xe2x80x9cI/Oxe2x80x9d connections for carrying signals and/or power to the chip.
The structures utilized to provide the xe2x80x9cfirst levelxe2x80x9d interconnection between a chip and the substrate should accommodate all of the electrical interconnections in a relatively compact region of the substrate. Moreover, the first level interconnection structures ordinarily are subject to strain caused by thermal cycling as temperatures in the assembly change. The electrical power dissipated within the chip tends to heat the chip and the substrate, so that temperatures of the chip and substrate rise and fall as the device is turned on and off. Differential thermal expansion of the chip and substrate cause the contacts on the chip to move relative to the connected electrical contact pads on the substrate during each heating and cooling cycle of the chip (xe2x80x9cthermal cyclingxe2x80x9d). This tends to cause fatigue of the elements connecting individual contacts and contact pads.
The chip package should be capable of dissipating the heat generated by operation so as to limit the temperature rise of the chip. Additionally, the chip package should provide physical protection to the chip and to the electrical connections between the chip and substrate. Thus, the package should protect the chip and the electrical interconnections from corrosion or other chemical damage. The cost of the chip and the substrate assemblies is also a concern. All of these factors, taken together, present a considerable engineering challenge.
One common approach to the chip mounting problem is referred to as a xe2x80x9cdie attach/wire bond package.xe2x80x9d The die attach/wire bond package, along with other alternatives, is generally described in Multichip Module-Technologies and Alternativesxe2x80x94The Basics: Doane and Franzon, eds. pp. 56-69. In the die attach/wire bond process, also referred to as a xe2x80x9cface upxe2x80x9d wire bond package or simply as a xe2x80x9cwire bondxe2x80x9d package the chip is placed on a substrate with the contact-bearing front face of the chip facing upwardly, away from the substrate. The rear face of the chip is bonded to the substrate by a material commonly referred to as a die bond material. Fine gold or aluminum wires are connected between individual contacts on the chip and individual contact pads on the substrate. The entire assembly may be contained in an outer package which is filled with an encapsulant or xe2x80x9cpottingxe2x80x9d compound such as a relatively soft silicone or other elastomer. Because the rear face of the chip is connected to the substrate by the die bond adhesive, the wire bond package provides reasonable thermal dissipation from the chip to the substrate. The individual chips must be handled in a xe2x80x9cbarexe2x80x9d or unpackaged condition during assembly to the substrate. This special handling, and the wire bonding process itself, require considerable care and special operations. However, typical die attach materials having very high thermal conductivity, such as silver or ceramic filled epoxies, are relatively stiff and noncompliant. When a continuous layer of such a material is applied between the chip and the substrate, it can fail during thermal cycling. Further, voids can occur in a layer of die attach material. Gases trapped in voids can cause failure of the package during service. Moreover, it is difficult to test any individual chip at full operating speed before the chip is mounted to the substrate.
As described in PCT International Publication WO 92/05582 and in U.S. Pat. No. 5,347,159, the disclosures of which are incorporated by reference herein, a semiconductor chip assembly may be provided with a flexible, sheet-like backing element overlying the rear face of the chip. Terminals on the backing element are connected to contacts on the front face of the chip, as by leads extending alongside the edges of the chip. A compliant layer may be provided between the terminals on the backing element and the chip itself, so that the terminals remain movable with respect to the chip. A cover may overlie the front of the chip and may be filled with an encapsulant. The entire assembly may be handled and mounted using essentially the same techniques as are used for surface mounting of conventional components on printed circuit boards. Thus, the terminals of the package can be bonded to contact pads on the substrate using masses of solder disposed between the terminals and contact pads. Prior to mounting, the chip assembly can be tested by engaging a test fixture with the terminals. Such a package typically provides relatively good thermal conductivity between the chip and the package so that the package can serve as a heat sink. However, such a package typically provides limited thermal conductivity between the chip and the substrate.
A chip package sold under the designation Micro-Star BGA by Sharp Corporation and by Texas Instruments, Inc. also includes a chip in a face-up disposition. A flexible polyimide film overlies the back surface of the chip. Wire bonds connect terminals on the front face of the chip to trace terminals on the flexible polyimide film. These terminals in turn can be bonded to a chip by solder balls. A die attach adhesive and a solder mask layer are interposed between the rear face of the chip and polyimide layer. The wire bonds and the chip are covered by a molded epoxy cover. Voids and delaminations in the die attach layer can cause rupture of such a package during thermal cycling. Moreover, such packages typically provide relatively low thermal conductivity from the chip to the substrate.
Additionally, encapsulated metallic conductors such as wire bonds are susceptible to fatigue failures. Typical wire bonds incorporate sharp corners and sharp changes in cross-sectional area at junctions between the fine bonding wire and the connected parts. For example, in a xe2x80x9cball-bond,xe2x80x9d each fine wire joins a relatively massive ball of wire material at one end. These features tend to create stress concentrations at the junctures. If the wire is flexed repeatedly during service, it can fail at such stress concentrations. Where the wire is encapsulated in a rigid material, differential thermal expansion of the chip and encapsulant can cause repeated flexure of the wire and fatigue failure. Attempts have been made to avoid such fatigue failures by using very soft encapsulants such as soft elastomers or gel. However, these attempts have not been entirely successful; fatigue failure of encapsulated wire bonds remains a significant problem, even with relatively soft encapsulants.
Accordingly, further improvements in microelectronic packaging would be desirable.
The present invention provides such further improvements. One aspect of the present invention provides a semiconductor chip assembly which includes a dielectric element, having top and bottom surfaces such as a flexible, sheetlike element. A semiconductor chip is mounted above the top surface of the dielectric element with the rear surface of the chip facing downwardly towards the dielectric element and with the front surface, bearing contacts, facing upwardly away from the dielectric element. A plurality of thermally conductive elements such as thermally conductive posts are disposed between the top surface of the dielectric element and the rear surface of the chip and most preferably these posts extend all the way from the top surface of the dielectric element to the rear surface of the chip. The dielectric element has terminals which are accessible from the bottom surface of the dielectric element so that the terminals can be connected to a substrate disposed beneath the dielectric element. Thus, the terminals may be disposed on the bottom surface, or may be accessible from the bottom surface through holes in the dielectric element. Appropriate means are provided for electrically connecting the contacts on the chip to the terminals. For example, flexible leads may extend between the contacts on the chip and conductive traces formed on the dielectric element. Thus, when the terminals are connected to contact pads on the substrate, the chip contacts are electrically connected to the contact pads of the substrate. The posts of the dielectric element and the terminals cooperatively provide a thermal conduction path from the rear face of the chip to the substrate.
Most preferably, the assembly includes a flexible rear encapsulant disposed between the rear surface of the chip and the top surface of the dielectric element, so that the rear encapsulant extends between the posts. The rear encapsulant and the posts preferably fill the space between the rear surface of the chip and the top surface of the dielectric element completely, so that there are no voids in such space. The posts desirably have some flexibility. Thus, the posts may be formed from a material such as a silver-filled epoxy or other metal-filled polymer. Even where a relatively stiff metal-filled polymer or other relatively stiff material is used, the configuration of the posts can be selected to provide reasonable flexibility and hence to permit movement of the dielectric element relative to the rear face of the chip. As discussed below, such relative movability allows compensation for thermal expansion and limits mechanical stresses in the system.
In a particularly preferred arrangement, some or all of the individual posts on the top surface of the dielectric element are disposed directly above corresponding terminals on the bottom surface of the dielectric element, so that each of these posts is directly aligned with the corresponding terminal. The aligned posts and terminals may be electrically connected to one another, or else may be separated from one another by a relatively thin dielectric layer such as a solder mask layer. In either case, the aligned posts and terminals provide a straight, low-resistance thermal path from the rear surface of the chip to the substrate when the terminals are bonded to contact pads on the substrate. In further preferred embodiments, a layer of a highly thermally conductive metal, such as copper, may be provided over the top surface of the dielectric element between the dielectric element and the individual posts to provide enhanced thermal dissipation from the chip to the substrate by providing an additional thermal conduction path. The dielectric element becomes relatively less flexible as the thickness of the layer of highly thermally conductive metal increases. The thermally conductive layer makes alignment of the posts and the solder masses less important because the layer provides horizontal conduction therebetween. The assembly thus provides good thermal dissipation from the chip to the substrate. This thermal dissipation is further aided by the rear encapsulant, which provides further thermal conductivity between the rear surface of the chip and the top surface of the dielectric element. The rear encapsulant has a thermal conductivity of approximately between about 1.0 to about 10.0 W/cm-xc2x0K.
A further aspect of the present invention provides a semiconductor chip assembly which also includes a dielectric element having top and bottom surfaces, the dielectric element having electrically conductive traces thereon. Here again, a semiconductor chip is disposed atop the dielectric element, with the rear surface of the chip facing the top surface of the dielectric element. Flexible leads extend from contacts on the front surface of the chip downwardly along side edges of the chip and join the traces on the dielectric element at bond points. The bond points are disposed in at least one edge region of the dielectric element. Each edge region is disposed alongside one edge of the chip. A dielectric encapsulant referred to herein as the xe2x80x9clead encapsulantxe2x80x9d surrounds the leads and the chip. Thus, portions of the lead encapsulant are disposed between the edges of the chip and the leads.
The bond points on each edge region are disposed in a row or rows parallel to the adjacent edge of the chip and parallel to a medial plane of the chip passing through the geometric center of the chip. The distance between each row of bond points and the adjacent edge of the chip is selected so that the sum of: (1) the product of (a) the coefficient of expansion of the lead encapsulant and (b) the distance between the edge of the chip and the ray of bond points and (2) the product of the coefficient of expansion of the chip and the distance from the medial plane of the chip to the edge of the chip is substantially equal to the product of the coefficient of expansion of the trace-bearing dielectric element and the distance between the medial plane of the chip and the bond points. As further discussed below, this relationship tends to minimize relative movement between the bond points and the immediately adjacent regions of the lead encapsulant upon thermal expansion or contraction of the assembly and thus tends to minimize repetitive stress in the leads at the bond points.
A further aspect of the invention provides a microelectronic assembly incorporating a chip or other microelectronic element having a front surface with contacts thereon and having flexible leads such as wire bonds extending from contacts on the front surface of the chip, the leads being connected to the contacts of joints on the front surface. Here again, a lead encapsulant, preferably a flexible encapsulant surrounds the leads and the chip. A spreader is disposed over the front surface of the chip and overlies the contacts and the adjacent regions of the lead encapsulant. Thus, the lead encapsulant extends between the chip front surface and the spreader. The spreader has a coefficient of thermal expansion close to the coefficient of thermal expansion of the chip or other microelectronic element and preferably substantially equal to the coefficient of thermal expansion of the chip. The spreader may serve as a physically protective packaging element and may also help to dissipate heat from the microelectronic element.
The spreader tends to suppress shear strain in the encapsulant in the vicinity of the contacts. Stated another way, expansion and contraction of the encapsulant are substantially constrained by the confronting surfaces of the microelectronic element and spreader. Upon heating or cooling of the assembly, the encapsulant surrounding each lead in the vicinity of the chip contact tends to move along with the contact. This minimizes shear stress in the lead at the contact. By contrast, if the encapsulant were constrained between a microelectronic element and a packaging element having coefficient of thermal expansion markedly different from that of the microelectronic element, significant shearing can occur in the encapsulant. As the encapsulant deforms in shear, it can impose significant flexual loads on the leads embedded therein. Such substantial loads can occur even if the encapsulant itself is soft. Indeed, substantial shearing loads can occur even if a soft encapsulant is unconstrained, if the encapsulant itself has a coefficient of thermal expansion substantially different from that of the microelectronic element.
In certain instances, it may be desirable to modify the shear strain which is present in the lead encapsulant. Thus, in preferred embodiments of the present invention, changes in the shear strain in the encapsulant in the vicinity of the contacts may be induced by changing the surface area of the spreader or changing the thermal mass of the spreader. For example, the surface area of the spreader confronting the chip contacts may be reduced which will, in turn, reduce the ability of the spreader to constrain the encapsulant in the vicinity of the contacts. Conversely, the thermal mass of the spreader may be increased to enhance the spreader""s ability to constrain the encapsulant in the vicinity of the contacts. Alternatively, the shear strain in the encapsulant in the vicinity of the contacts may be modified by changing the geometry or shape of the lead encapsulant itself, e.g. forming the encapsulant layer with sloped sidewalls.
A package according to the most preferred embodiments of the present invention incorporates the features of all of the aspects discussed above.
A further aspect of the invention provides a method of enhancing the reliability of electrical connections in a semiconductor package during operation of the chip. The method includes the steps of providing a semiconductor chip having a front contact bearing surface and a rear surface; providing flexible leads extending from the contacts on the front surface of the chip, the flexible leads being connected to the contacts at joints on the front surface; juxtaposing a spreader above the front surface, the spreader having a coefficient of thermal expansion substantially equal to the coefficient of thermal expansion of the chip; and disposing a liquid encapsulant between the front surface and the spreader and around the leads and curing the encapsulant, whereby the motion of the leads during thermal cycling is constrained.
The foregoing and other objects, features and advantages of the present invention would be more readily apparent from the detailed description of the preferred embodiments set forth below, taken in conjunction with the accompanying drawings.